[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"project-senior-npu-kernel-operator-engineer":3,"similar-senior-npu-kernel-operator-engineer":32},{"id":4,"slug":5,"title":6,"skills":7,"budget":20,"duration":20,"location":20,"onsitePercent":20,"contractType":21,"foundAt":22,"category":23,"description":27,"rawText":28,"webTitle":6,"webText":29,"language":30,"projectId":20,"sourceUrl":31},9009,"senior-npu-kernel-operator-engineer","Senior NPU Kernel \u002F Operator Engineer",[8,9,10,11,12,13,14,15,16,17,18,19],"C\u002FC++","Python","Tensor computation","Neural network operators","Memory hierarchy","Bandwidth and latency analysis","Cache\u002FSRAM behaviour","Parallelism and synchronization","Data locality and vectorization","Performance optimization","Accelerator programming","GPU\u002FNPU development",null,"permanent","2026-06-03T05:31:14+00:00",{"id":24,"slug":25,"label":26},3,"ai_ml","AI & Machine Learning","Entwicklung und Optimierung von hochperformanten Deep Learning Operatoren für eine AI-Accelerator-Plattform. Fokus auf Kernel-Design, Hardware-bewusste Performance-Optimierung und Korrektheitsprüfung. Arbeit an der Schnittstelle von AI-Systemen, Compiler-Optimierung und Hardware-Beschleunigung.","\u003Cdiv class=\"flex max-w-full flex-col gap-4 grow\">\n\u003Cdiv class=\"min-h-8 text-message relative flex w-full flex-col items-end gap-2 text-start break-words whitespace-normal outline-none keyboard-focused:focus-ring [.text-message+&]:mt-1\" dir=\"auto\" data-message-author-role=\"assistant\" data-message-id=\"1aad0b8b-68c6-4d77-88bb-eacf037d9948\" data-message-model-slug=\"gpt-5-5\" data-turn-start-message=\"true\">\n\u003Cdiv class=\"flex w-full flex-col gap-1 empty:hidden\">\n\u003Cdiv class=\"markdown prose dark:prose-invert wrap-break-word w-full dark markdown-new-styling\">\n\u003Ch1 data-section-id=\"thj0q4\" data-start=\"155\" data-end=\"194\">Senior NPU Kernel \u002F Operator Engineer\u003C\u002Fh1>\n\u003Ch2 data-section-id=\"rzkdgm\" data-start=\"196\" data-end=\"207\">Overview\u003C\u002Fh2>\n\u003Cp data-start=\"209\" data-end=\"403\">We are seeking a \u003Cstrong data-start=\"226\" data-end=\"267\">Senior NPU Kernel \u002F Operator Engineer\u003C\u002Fstrong> to lead the development and optimization of high-performance deep learning operators for a next-generation \u003Cstrong data-start=\"375\" data-end=\"402\">AI accelerator platform\u003C\u002Fstrong>.\u003C\u002Fp>\n\u003Cp data-start=\"405\" data-end=\"556\">This role focuses on \u003Cstrong data-start=\"426\" data-end=\"506\">kernel design, hardware-aware performance tuning, and correctness validation\u003C\u002Fstrong> across a broad range of neural network workloads.\u003C\u002Fp>\n\u003Cp data-start=\"558\" data-end=\"823\">The ideal candidate will have deep experience optimizing compute-intensive software on \u003Cstrong data-start=\"645\" data-end=\"726\">GPU, NPU, DSP, SIMD, embedded accelerators, compiler backends, or HPC systems\u003C\u002Fstrong>, with the ability to reason from model-level requirements down to hardware execution efficiency.\u003C\u002Fp>\n\u003Chr data-start=\"825\" data-end=\"828\" \u002F>\n\u003Ch2 data-section-id=\"r8dte7\" data-start=\"830\" data-end=\"849\">Responsibilities\u003C\u002Fh2>\n\u003Cul data-start=\"851\" data-end=\"2246\">\n\u003Cli data-section-id=\"1re3mk7\" data-start=\"851\" data-end=\"1063\">Design, implement, and optimize high-performance operators such as:\n\u003Cul data-start=\"923\" data-end=\"1063\">\n\u003Cli data-section-id=\"7vf5at\" data-start=\"923\" data-end=\"938\">Normalization\u003C\u002Fli>\n\u003Cli data-section-id=\"s3cihd\" data-start=\"941\" data-end=\"952\">Reduction\u003C\u002Fli>\n\u003Cli data-section-id=\"y2fiaj\" data-start=\"955\" data-end=\"966\">Transpose\u003C\u002Fli>\n\u003Cli data-section-id=\"julpw0\" data-start=\"969\" data-end=\"978\">Reshape\u003C\u002Fli>\n\u003Cli data-section-id=\"1og16cs\" data-start=\"981\" data-end=\"999\">Gather \u002F Scatter\u003C\u002Fli>\n\u003Cli data-section-id=\"1fncdvq\" data-start=\"1002\" data-end=\"1033\">Quantization \u002F Dequantization\u003C\u002Fli>\n\u003Cli data-section-id=\"1xx8sfr\" data-start=\"1036\" data-end=\"1063\">Fused elementwise kernels\u003C\u002Fli>\n\u003C\u002Ful>\n\u003C\u002Fli>\n\u003Cli data-section-id=\"tuy109\" data-start=\"1065\" data-end=\"1255\">Own performance optimization across key hardware constraints, including:\n\u003Cul data-start=\"1142\" data-end=\"1255\">\n\u003Cli data-section-id=\"9ys4qu\" data-start=\"1142\" data-end=\"1160\">Memory bandwidth\u003C\u002Fli>\n\u003Cli data-section-id=\"1osbob3\" data-start=\"1163\" data-end=\"1181\">SRAM utilization\u003C\u002Fli>\n\u003Cli data-section-id=\"3uz58s\" data-start=\"1184\" data-end=\"1196\">Data reuse\u003C\u002Fli>\n\u003Cli data-section-id=\"1d47zl4\" data-start=\"1199\" data-end=\"1212\">DMA latency\u003C\u002Fli>\n\u003Cli data-section-id=\"xha4ln\" data-start=\"1215\" data-end=\"1231\">Bank conflicts\u003C\u002Fli>\n\u003Cli data-section-id=\"xg0oaf\" data-start=\"1234\" data-end=\"1255\">Compute utilization\u003C\u002Fli>\n\u003C\u002Ful>\n\u003C\u002Fli>\n\u003Cli data-section-id=\"gnmpxi\" data-start=\"1257\" data-end=\"1374\">Develop advanced optimization strategies including:\n\u003Cul data-start=\"1313\" data-end=\"1374\">\n\u003Cli data-section-id=\"5mblcp\" data-start=\"1313\" data-end=\"1321\">Tiling\u003C\u002Fli>\n\u003Cli data-section-id=\"14kgxtt\" data-start=\"1324\" data-end=\"1334\">Blocking\u003C\u002Fli>\n\u003Cli data-section-id=\"1wwl43j\" data-start=\"1337\" data-end=\"1352\">Vectorization\u003C\u002Fli>\n\u003Cli data-section-id=\"182x7t\" data-start=\"1355\" data-end=\"1374\">Memory scheduling\u003C\u002Fli>\n\u003C\u002Ful>\n\u003C\u002Fli>\n\u003Cli data-section-id=\"10rltuo\" data-start=\"1376\" data-end=\"1516\">Analyze and resolve bottlenecks related to:\n\u003Cul data-start=\"1424\" data-end=\"1516\">\n\u003Cli data-section-id=\"47zvni\" data-start=\"1424\" data-end=\"1442\">Memory hierarchy\u003C\u002Fli>\n\u003Cli data-section-id=\"816qos\" data-start=\"1445\" data-end=\"1471\">Synchronization overhead\u003C\u002Fli>\n\u003Cli data-section-id=\"1w268j4\" data-start=\"1474\" data-end=\"1498\">Instruction scheduling\u003C\u002Fli>\n\u003Cli data-section-id=\"pydynv\" data-start=\"1501\" data-end=\"1516\">Data movement\u003C\u002Fli>\n\u003C\u002Ful>\n\u003C\u002Fli>\n\u003Cli data-section-id=\"1lon4za\" data-start=\"1518\" data-end=\"1629\">Validate operator correctness and numerical precision against reference implementations (e.g. PyTorch, NumPy)\u003C\u002Fli>\n\u003Cli data-section-id=\"2aksud\" data-start=\"1631\" data-end=\"1744\">Benchmark and profile kernel performance across simulation, emulation, FPGA, or production silicon environments\u003C\u002Fli>\n\u003Cli data-section-id=\"11ch6yi\" data-start=\"1746\" data-end=\"1872\">Debug complex issues involving:\n\u003Cul data-start=\"1782\" data-end=\"1872\">\n\u003Cli data-section-id=\"6qmbw0\" data-start=\"1782\" data-end=\"1798\">Tensor layouts\u003C\u002Fli>\n\u003Cli data-section-id=\"nk3sil\" data-start=\"1801\" data-end=\"1817\">Precision loss\u003C\u002Fli>\n\u003Cli data-section-id=\"np1i6u\" data-start=\"1820\" data-end=\"1844\">Memory access patterns\u003C\u002Fli>\n\u003Cli data-section-id=\"4ayqi4\" data-start=\"1847\" data-end=\"1872\">Performance regressions\u003C\u002Fli>\n\u003C\u002Ful>\n\u003C\u002Fli>\n\u003Cli data-section-id=\"1xrksoy\" data-start=\"1874\" data-end=\"1955\">Build performance models and optimize operators toward hardware roofline limits\u003C\u002Fli>\n\u003Cli data-section-id=\"17sfee4\" data-start=\"1957\" data-end=\"2094\">Collaborate closely with compiler, runtime, hardware architecture, and ML model teams to improve operator APIs and execution efficiency\u003C\u002Fli>\n\u003Cli data-section-id=\"z5o98r\" data-start=\"2096\" data-end=\"2176\">Document optimization strategies, tensor layouts, and performance improvements\u003C\u002Fli>\n\u003Cli data-section-id=\"ed9gbq\" data-start=\"2178\" data-end=\"2246\">Mentor junior engineers and help define engineering best practices\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Chr data-start=\"2248\" data-end=\"2251\" \u002F>\n\u003Ch2 data-section-id=\"htanpl\" data-start=\"2253\" data-end=\"2268\">Requirements\u003C\u002Fh2>\n\u003Cul data-start=\"2270\" data-end=\"3220\">\n\u003Cli data-section-id=\"1lhe4qi\" data-start=\"2270\" data-end=\"2373\">BS \u002F MS \u002F PhD in \u003Cstrong data-start=\"2289\" data-end=\"2355\">Computer Science, Electrical Engineering, Computer Engineering\u003C\u002Fstrong>, or related field\u003C\u002Fli>\n\u003Cli data-section-id=\"1q6iqo2\" data-start=\"2375\" data-end=\"2604\">\u003Cstrong data-start=\"2377\" data-end=\"2389\">5+ years\u003C\u002Fstrong> of experience in one or more of the following:\n\u003Cul data-start=\"2439\" data-end=\"2604\">\n\u003Cli data-section-id=\"sul5ly\" data-start=\"2439\" data-end=\"2464\">Accelerator programming\u003C\u002Fli>\n\u003Cli data-section-id=\"jjat7h\" data-start=\"2467\" data-end=\"2490\">GPU \u002F NPU development\u003C\u002Fli>\n\u003Cli data-section-id=\"1hjhedy\" data-start=\"2493\" data-end=\"2523\">Compiler backend engineering\u003C\u002Fli>\n\u003Cli data-section-id=\"4dm4gg\" data-start=\"2526\" data-end=\"2544\">Embedded systems\u003C\u002Fli>\n\u003Cli data-section-id=\"9fyg3n\" data-start=\"2547\" data-end=\"2575\">High-performance computing\u003C\u002Fli>\n\u003Cli data-section-id=\"itb3bl\" data-start=\"2578\" data-end=\"2604\">Performance optimization\u003C\u002Fli>\n\u003C\u002Ful>\n\u003C\u002Fli>\n\u003Cli data-section-id=\"2u71qe\" data-start=\"2606\" data-end=\"2666\">Strong programming skills in:\n\u003Cul data-start=\"2640\" data-end=\"2666\">\n\u003Cli data-section-id=\"cbyf\" data-start=\"2640\" data-end=\"2651\">\u003Cstrong data-start=\"2642\" data-end=\"2651\">C\u002FC++\u003C\u002Fstrong>\u003C\u002Fli>\n\u003Cli data-section-id=\"1r2ptz0\" data-start=\"2654\" data-end=\"2666\">\u003Cstrong data-start=\"2656\" data-end=\"2666\">Python\u003C\u002Fstrong>\u003C\u002Fli>\n\u003C\u002Ful>\n\u003C\u002Fli>\n\u003Cli data-section-id=\"1swq8ij\" data-start=\"2668\" data-end=\"2744\">Deep understanding of:\n\u003Cul data-start=\"2695\" data-end=\"2744\">\n\u003Cli data-section-id=\"1rb43hw\" data-start=\"2695\" data-end=\"2715\">Tensor computation\u003C\u002Fli>\n\u003Cli data-section-id=\"qc7hvo\" data-start=\"2718\" data-end=\"2744\">Neural network operators\u003C\u002Fli>\n\u003C\u002Ful>\n\u003C\u002Fli>\n\u003Cli data-section-id=\"frev7n\" data-start=\"2746\" data-end=\"2954\">Strong knowledge of computer architecture concepts:\n\u003Cul data-start=\"2802\" data-end=\"2954\">\n\u003Cli data-section-id=\"47zvni\" data-start=\"2802\" data-end=\"2820\">Memory hierarchy\u003C\u002Fli>\n\u003Cli data-section-id=\"p527sm\" data-start=\"2823\" data-end=\"2855\">Bandwidth and latency analysis\u003C\u002Fli>\n\u003Cli data-section-id=\"crzo7z\" data-start=\"2858\" data-end=\"2882\">Cache \u002F SRAM behaviour\u003C\u002Fli>\n\u003Cli data-section-id=\"6zy7ot\" data-start=\"2885\" data-end=\"2918\">Parallelism and synchronization\u003C\u002Fli>\n\u003Cli data-section-id=\"1ep4iml\" data-start=\"2921\" data-end=\"2954\">Data locality and vectorization\u003C\u002Fli>\n\u003C\u002Ful>\n\u003C\u002Fli>\n\u003Cli data-section-id=\"1k4ye5v\" data-start=\"2956\" data-end=\"3046\">Proven experience optimizing performance-critical kernels or numerical compute pipelines\u003C\u002Fli>\n\u003Cli data-section-id=\"pdsokz\" data-start=\"3048\" data-end=\"3150\">Ability to identify and resolve performance bottlenecks from algorithm through to hardware execution\u003C\u002Fli>\n\u003Cli data-section-id=\"15it0ea\" data-start=\"3152\" data-end=\"3220\">Strong debugging, profiling, and analytical problem-solving skills\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Chr data-start=\"3222\" data-end=\"3225\" \u002F>\n\u003Ch2 data-section-id=\"6t85pa\" data-start=\"3227\" data-end=\"3250\">Preferred Experience\u003C\u002Fh2>\n\u003Cp data-start=\"3252\" data-end=\"3297\">Experience with one or more of the following:\u003C\u002Fp>\n\u003Ch3 data-section-id=\"i8toce\" data-start=\"3299\" data-end=\"3323\">Frameworks \u002F Tooling\u003C\u002Fh3>\n\u003Cul data-start=\"3324\" data-end=\"3370\">\n\u003Cli data-section-id=\"1j40yor\" data-start=\"3324\" data-end=\"3330\">CUDA\u003C\u002Fli>\n\u003Cli data-section-id=\"5fwrte\" data-start=\"3331\" data-end=\"3339\">Triton\u003C\u002Fli>\n\u003Cli data-section-id=\"1sstrn7\" data-start=\"3340\" data-end=\"3348\">OpenCL\u003C\u002Fli>\n\u003Cli data-section-id=\"1o4rhj\" data-start=\"3349\" data-end=\"3354\">TVM\u003C\u002Fli>\n\u003Cli data-section-id=\"1j3yz8y\" data-start=\"3355\" data-end=\"3361\">MLIR\u003C\u002Fli>\n\u003Cli data-section-id=\"1moujd1\" data-start=\"3362\" data-end=\"3370\">Halide\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Ch3 data-section-id=\"1ppl73i\" data-start=\"3372\" data-end=\"3394\">Systems Experience\u003C\u002Fh3>\n\u003Cul data-start=\"3395\" data-end=\"3481\">\n\u003Cli data-section-id=\"1j4cn97\" data-start=\"3395\" data-end=\"3401\">SIMD\u003C\u002Fli>\n\u003Cli data-section-id=\"1o4f2n\" data-start=\"3402\" data-end=\"3407\">DSP\u003C\u002Fli>\n\u003Cli data-section-id=\"fzc9ft\" data-start=\"3408\" data-end=\"3424\">Embedded C\u002FC++\u003C\u002Fli>\n\u003Cli data-section-id=\"pt5fcn\" data-start=\"3425\" data-end=\"3448\">GPU \u002F NPU programming\u003C\u002Fli>\n\u003Cli data-section-id=\"17krj4b\" data-start=\"3449\" data-end=\"3467\">FPGA development\u003C\u002Fli>\n\u003Cli data-section-id=\"9z861x\" data-start=\"3468\" data-end=\"3481\">HPC systems\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Ch3 data-section-id=\"1r0vk2e\" data-start=\"3483\" data-end=\"3519\">Advanced Optimization Techniques\u003C\u002Fh3>\n\u003Cul data-start=\"3520\" data-end=\"3642\">\n\u003Cli data-section-id=\"137grgb\" data-start=\"3520\" data-end=\"3541\">Tiling and blocking\u003C\u002Fli>\n\u003Cli data-section-id=\"1wwl43j\" data-start=\"3542\" data-end=\"3557\">Vectorization\u003C\u002Fli>\n\u003Cli data-section-id=\"clc40c\" data-start=\"3558\" data-end=\"3586\">Memory access optimization\u003C\u002Fli>\n\u003Cli data-section-id=\"1w268j4\" data-start=\"3587\" data-end=\"3611\">Instruction scheduling\u003C\u002Fli>\n\u003Cli data-section-id=\"1ozu69b\" data-start=\"3612\" data-end=\"3642\">Mixed-precision optimization\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Ch3 data-section-id=\"2q4qr4\" data-start=\"3644\" data-end=\"3665\">Numerical Formats\u003C\u002Fh3>\n\u003Cul data-start=\"3666\" data-end=\"3706\">\n\u003Cli data-section-id=\"1j467fj\" data-start=\"3666\" data-end=\"3672\">FP32\u003C\u002Fli>\n\u003Cli data-section-id=\"1j467h5\" data-start=\"3673\" data-end=\"3679\">FP16\u003C\u002Fli>\n\u003Cli data-section-id=\"1j42tl7\" data-start=\"3680\" data-end=\"3686\">BF16\u003C\u002Fli>\n\u003Cli data-section-id=\"1o4juu\" data-start=\"3687\" data-end=\"3692\">FP8\u003C\u002Fli>\n\u003Cli data-section-id=\"uiu2q3\" data-start=\"3693\" data-end=\"3706\">INT8 \u002F INT4\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Ch3 data-section-id=\"wmb63h\" data-start=\"3708\" data-end=\"3751\">AI Accelerator Architecture Familiarity\u003C\u002Fh3>\n\u003Cul data-start=\"3752\" data-end=\"3845\">\n\u003Cli data-section-id=\"638sem\" data-start=\"3752\" data-end=\"3768\">Matrix engines\u003C\u002Fli>\n\u003Cli data-section-id=\"1obs98\" data-start=\"3769\" data-end=\"3785\">Vector engines\u003C\u002Fli>\n\u003Cli data-section-id=\"1jusf8m\" data-start=\"3786\" data-end=\"3803\">Systolic arrays\u003C\u002Fli>\n\u003Cli data-section-id=\"2309p9\" data-start=\"3804\" data-end=\"3817\">DMA engines\u003C\u002Fli>\n\u003Cli data-section-id=\"1tf2qp7\" data-start=\"3818\" data-end=\"3845\">SRAM \u002F NoC \u002F DRAM systems\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Ch3 data-section-id=\"6xc137\" data-start=\"3847\" data-end=\"3856\">Bonus\u003C\u002Fh3>\n\u003Cul data-start=\"3857\" data-end=\"3921\">\n\u003Cli data-section-id=\"uv7rzj\" data-start=\"3857\" data-end=\"3921\">Experience with simulator, emulator, FPGA, or silicon bring-up\u003C\u002Fli>\n\u003C\u002Ful>\n\u003Chr data-start=\"3923\" data-end=\"3926\" \u002F>\n\u003Ch3 data-section-id=\"pshfun\" data-start=\"3928\" data-end=\"3943\">Opportunity\u003C\u002Fh3>\n\u003Cp data-start=\"3945\" data-end=\"4279\" data-is-last-node=\"\" data-is-only-node=\"\">Join a highly technical team building cutting-edge AI compute infrastructure and contribute directly to the performance of next-generation machine learning hardware. This is an opportunity to work at the intersection of \u003Cstrong data-start=\"4165\" data-end=\"4229\">AI systems, compiler optimisation, and hardware acceleration\u003C\u002Fstrong>, with significant ownership and technical impact.\u003C\u002Fp>\n\u003C\u002Fdiv>\n\u003C\u002Fdiv>\n\u003C\u002Fdiv>\n\u003C\u002Fdiv>\n\u003Cdiv class=\"z-0 flex min-h-[46px] justify-start\"> \u003C\u002Fdiv>\n\u003Cdiv class=\"mt-3 w-full empty:hidden\"> \u003C\u002Fdiv>\n\u003Cp>Darwin Recruitment is acting as an Employment Agency in relation to this vacancy.\u003C\u002Fp>\n\u003Cp>\u003Cimg src=\"https:\u002F\u002Fcounter.adcourier.com\u002FUmVlY2UuV2FsZG9uLjczMjY5LjEyNzg0QGRhcndpbi5hcGxpdHJhay5jb20.gif\">\u003C\u002Fp>\n\u003Cp>\u003Cspan style=\"color: #ffffff\">Reece Waldon\u003C\u002Fspan>\u003C\u002Fp>\nAnsprechpartner: Reece Waldon\nE-Mail: Reece.Waldon@darwinrecruitment.com\nTelefon: +44 1277 287285","Wir suchen einen Senior NPU Kernel \u002F Operator Engineer zur Leitung der Entwicklung und Optimierung hochperformanter Deep Learning Operatoren für eine Next-Generation AI-Accelerator-Plattform. Diese Position konzentriert sich auf Kernel-Design, hardware-bewusste Performance-Optimierung und Korrektheitsprüfung über ein breites Spektrum von Neural Network Workloads.\n\nZu den Hauptaufgaben gehören die Entwicklung und Optimierung von High-Performance-Operatoren wie Normalization, Reduction, Transpose, Reshape, Gather\u002FScatter, Quantization\u002FDequantization und Fused Elementwise Kernels. Sie verantworten die Performance-Optimierung unter Berücksichtigung kritischer Hardware-Constraints wie Memory Bandwidth, SRAM-Nutzung, Data Reuse, DMA-Latenz und Compute Utilization.\n\nDie Rolle umfasst die Entwicklung fortgeschrittener Optimierungsstrategien einschließlich Tiling, Blocking, Vectorization und Memory Scheduling. Sie analysieren und lösen Bottlenecks in Bezug auf Memory Hierarchy, Synchronization Overhead und Data Movement. Die Validierung der Operator-Korrektheit gegen Referenzimplementierungen sowie Benchmarking und Profiling in verschiedenen Umgebungen gehören ebenfalls zu Ihren Aufgaben.\n\nWir erwarten einen Abschluss in Computer Science, Electrical Engineering oder verwandten Bereichen sowie mindestens 5 Jahre Erfahrung in Accelerator Programming, GPU\u002FNPU Development, Compiler Backend Engineering oder High-Performance Computing. Starke Programmierkenntnisse in C\u002FC++ und Python sowie tiefes Verständnis von Tensor Computation und Neural Network Operatoren sind erforderlich.\n\nErfahrung mit CUDA, Triton, OpenCL, TVM, MLIR, Halide oder SIMD\u002FDSP-Systemen ist von Vorteil. Die Position bietet die Möglichkeit, an der Spitze der AI-Hardware-Entwicklung zu arbeiten und die Zukunft des maschinellen Lernens mitzugestalten.","en","https:\u002F\u002Fwww.darwinrecruitment.com\u002Fjob\u002F8732695439294-senior-npu-kernel-operator-engineer-san-jose-california\u002F",{"items":33},[34,51,66,77,92,107,124,147,168,179,189,207,225,243,264],{"id":35,"slug":36,"title":37,"skills":38,"budget":20,"duration":20,"location":20,"onsitePercent":20,"contractType":48,"foundAt":49,"category":50},10464,"computer-vision-engineer-for-robotics-perception-stack","Computer Vision Engineer for Robotics Perception Stack",[39,40,41,42,43,44,45,46,47],"Computer vision","Sensor fusion","LiDAR","Cameras","PyTorch","TensorFlow","Object detection","Tracking","Scene understanding","contracting","2026-06-03T06:06:17+00:00",{"id":24,"slug":25,"label":26},{"id":52,"slug":53,"title":54,"skills":55,"budget":20,"duration":20,"location":20,"onsitePercent":20,"contractType":48,"foundAt":64,"category":65},10449,"infrastructure-engineer-for-distributed-model-training","Infrastructure Engineer for Distributed Model Training",[56,57,58,59,60,61,62,63],"PyTorch Distributed","Ray","CUDA","HPC networking","InfiniBand","RDMA","GPU computing","LLM training pipelines","2026-06-03T06:06:04+00:00",{"id":24,"slug":25,"label":26},{"id":67,"slug":68,"title":69,"skills":70,"budget":20,"duration":20,"location":20,"onsitePercent":20,"contractType":48,"foundAt":75,"category":76},10417,"ai-hardware-security-engineer-2","AI Hardware Security Engineer",[71,72,73,74],"Secure firmware","Hardware root of trust","Trusted execution environments","Low-level systems programming","2026-06-03T06:05:34+00:00",{"id":24,"slug":25,"label":26},{"id":78,"slug":79,"title":80,"skills":81,"budget":20,"duration":20,"location":20,"onsitePercent":20,"contractType":48,"foundAt":90,"category":91},10401,"ai-inference-platform-engineer-confidential-computing","AI Inference Platform Engineer - Confidential Computing",[82,83,84,85,86,87,88,89],"Kubernetes","GPU clusters","Confidential computing","Rust","Go","C++","AI inference","ML infrastructure","2026-06-03T06:05:20+00:00",{"id":24,"slug":25,"label":26},{"id":93,"slug":94,"title":95,"skills":96,"budget":20,"duration":20,"location":20,"onsitePercent":20,"contractType":48,"foundAt":105,"category":106},10385,"confidential-ai-systems-engineer-with-tee-expertise","Confidential AI Systems Engineer with TEE expertise",[97,98,99,100,101,102,103,43,58,104],"TEEs","SGX","SEV","TrustZone","Secure boot","Hardware attestation","Confidential containers","AI workloads","2026-06-03T06:05:04+00:00",{"id":24,"slug":25,"label":26},{"id":108,"slug":109,"title":110,"skills":111,"budget":20,"duration":119,"location":120,"onsitePercent":121,"contractType":48,"foundAt":122,"category":123},10341,"ai-engineer-llm-and-rag-systems","AI Engineer - LLM and RAG Systems",[9,112,113,114,115,116,117,118],"LLMs","RAG","embeddings","prompt engineering","AWS","vector databases","microservices","3 Monate (Verlängerung erwartet, ~1 Jahr Gesamtlaufzeit)","Utrecht",50,"2026-06-03T06:04:26+00:00",{"id":24,"slug":25,"label":26},{"id":125,"slug":126,"title":127,"skills":128,"budget":20,"duration":20,"location":144,"onsitePercent":121,"contractType":48,"foundAt":145,"category":146},8140,"ai-and-telco-architect","AI and Telco Architect",[129,130,131,132,133,134,135,136,137,138,139,140,141,142,143],"OSS","Assurance","Fulfillment","Inventory","Fault management","Capacity planning","AI\u002FML technologies","Real-time telemetry","Streaming technologies","Kafka","gNMI","OpenTelemetry","Enterprise architecture","Integration","Stakeholder communication","Netherlands","2026-06-03T05:07:08+00:00",{"id":24,"slug":25,"label":26},{"id":148,"slug":149,"title":150,"skills":151,"budget":163,"duration":20,"location":164,"onsitePercent":165,"contractType":21,"foundAt":166,"category":167},7744,"senior-gpu-systems-ai-infrastructure-engineer-nyc","Senior GPU Systems \u002F AI Infrastructure Engineer (NYC)",[152,153,154,155,87,85,9,43,156,157,158,57,159,160,161,162],"CUDA programming","GPU kernel optimization","parallel computing","distributed systems","JAX","NCCL","MPI","performance profiling","Nsight","Triton","HIP","Competitive + equity","New York City",75,"2026-06-03T04:48:20+00:00",{"id":24,"slug":25,"label":26},{"id":169,"slug":170,"title":171,"skills":172,"budget":20,"duration":20,"location":20,"onsitePercent":20,"contractType":48,"foundAt":177,"category":178},7629,"ai-compute-cluster-engineer","AI Compute Cluster Engineer",[59,82,173,174,175,176],"GPU scheduling","AI compute clusters","networking optimization","storage optimization","2026-06-03T04:37:11+00:00",{"id":24,"slug":25,"label":26},{"id":180,"slug":181,"title":182,"skills":183,"budget":185,"duration":20,"location":186,"onsitePercent":121,"contractType":21,"foundAt":187,"category":188},7608,"ai-telco-architect","AI Telco Architect",[129,130,131,132,133,134,135,136,137,138,139,140,141,184],"Integration experience","up to 90,000 EUR\u002Fyear","Amsterdam","2026-06-03T03:53:26+00:00",{"id":24,"slug":25,"label":26},{"id":190,"slug":191,"title":192,"skills":193,"budget":20,"duration":202,"location":203,"onsitePercent":204,"contractType":48,"foundAt":205,"category":206},7605,"ai-fullstack-engineer","AI Fullstack Engineer",[194,195,196,9,197,112,198,199,200,201],"React","TypeScript","Java","AI\u002FML","AI agents","LangChain","Vector Databases","Fullstack development","Initial 3 Months","Berlin",0,"2026-06-03T03:52:36+00:00",{"id":24,"slug":25,"label":26},{"id":208,"slug":209,"title":210,"skills":211,"budget":221,"duration":20,"location":222,"onsitePercent":20,"contractType":21,"foundAt":223,"category":224},7562,"ai-spezialist-mwd-ai-specialist","AI Spezialist (m\u002Fw\u002Fd) – AI Specialist",[9,212,213,214,215,216,116,217,218,219,220],"R","KI-Tools","Machine Learning","Datenverarbeitung","Cloud-Technologien","Azure","Google Cloud","Datenschutz","Compliance","mindestens 75.000 EUR\u002FJahr","Wien","2026-06-03T00:01:40+00:00",{"id":24,"slug":25,"label":26},{"id":226,"slug":227,"title":228,"skills":229,"budget":20,"duration":20,"location":239,"onsitePercent":240,"contractType":21,"foundAt":241,"category":242},7518,"manager-ki-und-prozessautomatisierung-mwd","Manager KI und Prozessautomatisierung (m\u002Fw\u002Fd)",[230,231,232,233,217,234,235,236,237,238],"KI","Prozessautomatisierung","Microsoft Copilot","Power Automate","ERP-Integration","SAP","Change Management","Digitalisierung","Large Language Models","Stephanskirchen",100,"2026-06-02T14:26:02+00:00",{"id":24,"slug":25,"label":26},{"id":244,"slug":245,"title":246,"skills":247,"budget":20,"duration":260,"location":20,"onsitePercent":261,"contractType":48,"foundAt":262,"category":263},7433,"ai-data-engineer-im-bereich-wissensmanagement-bots","AI Data Engineer im Bereich Wissensmanagement Bots",[248,9,249,250,251,252,253,138,254,255,256,257,258,259,216],"PostgreSQL","ETL\u002FELT-Pipelines","Big Data","SQL","Airflow","dbt","Spark","Data Engineering","Pandas","PySpark","Data Quality","Observability","6M+",20,"2026-06-02T09:30:40+00:00",{"id":24,"slug":25,"label":26},{"id":265,"slug":266,"title":267,"skills":268,"budget":20,"duration":20,"location":222,"onsitePercent":121,"contractType":48,"foundAt":273,"category":274},7414,"machine-learning-engineer-mwd","Machine Learning Engineer (m\u002Fw\u002Fd)",[214,44,43,9,212,269,116,218,270,271,272],"Apache Airflow","Datenmanagement","NLP","Computer Vision","2026-06-02T08:26:02+00:00",{"id":24,"slug":25,"label":26}]